The growing complexity and shrinking geometries of modern device technologies are making high-density, low-voltage devices increasingly susceptible to influences from electrical noise, process variation, and natural radiation interference. System-level effects of these errors can be far reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research direction (including nanotechnology). We are interested in soliciting papers that cover system-level effects of errors from a variety of perspectives: architectural, logical and circuit-level, and semiconductor processes. Case studies are also solicited.