A modern chip often contains large numbers of pre-designed macros (e.g., embedded memories, IP blocks) and standard cells of very different sizes. The fast-growing design complexity with large-scale mixed-size macros and standard cells has incurred significant challenges to modern circuit placement. In this talk, we first survey published techniques for modern circuit placement and then present our recent techniques for simultaneous large macro and standard cell placement. We also discuss the strengths and weaknesses of existing techniques for modern circuit placement. Finally, we provide some future research directions for modern circuit placement.