Falsification of nonlinear analog circuits is a very challenging problem. We utilize Rapidly-exploring Random Tree algorithm to generate tests for analog circuits. We present a methodology to generate goal-oriented test cases for verifying nonlinear analog circuits. We use a learning based approach to identify the goal regions in circuit’s state space. We use the information that we learn to guide the growth of Rapidly-exploring Random Trees (RRTs) towards these goal regions. Compared to previous approaches for test generation, our methodology generates several test cases of the circuit that are more concentrated in the relevant operating regions.
Seyed Nematollah Ahmadyan received the B.S. and M.S. degrees in Computer Engineering from the Sharif University of Technology, Tehran, Iran, in 2009 and 2011, respectively. He is currently pursuing the Ph.D. degree from the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign. His advisor is Prof. Shobha Vasudevan. His current research interest includes formal and semi-formal techniques for verification of analog circuits.