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NIma Honarmand (University of Illinois)
Siebel Center 2405
Illinois-Intel Parallelism Center
Illinois-Intel Parallelism Center (I2PC) Distinguished Speaker Series
Thursday, January 24th, 4-5pm CST, Siebel Center 2405
Cyrus: Unintrusive Application-Level Record-Replay for Replay Parallelism
University of Illinois
ABSTRACT: Architectures for deterministic record-replay (R&R) of multithreaded codes are attractive for program debugging, intrusion analysis, and fault-tolerance uses. However, very few of the proposed designs have focused on maximizing replay speed -- a key enabling property of these systems. In addition, those that have, require intrusive hardware or software modifications, or target whole-system R&R rather than the more useful application-level R&R. This paper presents the first hardware-based scheme for unintrusive, application-level R&R that explicitly targets high replay speed. Our scheme, called Cyrus, requires no modification to commodity snoopy cache coherence. It introduces the concept of an on-the-fly software Backend Pass during recording which, as the log is being generated, transforms it for high replay parallelism. This pass also fixes-up the log, and can flexibly trade-off replay parallelism for log size. We analyze the performance of Cyrus using full system (OS plus hardware) simulation. Our results show that Cyrus has negligible recording overhead. In addition, for 8-processor runs of SPLASH-2, Cyrus attains an average replay parallelism of 5, and a replay speed that is, on average, only about 50% lower than the recording speed.
This is joint work with Nathan Dautenhahn, Samuel King, Josep Torrellas (UIUC), Gilles Pokam and Cristiano Pereira (Intel, Santa Clara) and will appear in ASPLOS 2013.
BIO: Nima Honarmand is a PhD student in the iacoma group at the Computer Science Department of the University of Illinois at Urbana-Champaign. He received his Master's degree from the University of Tehran and his Bachelor's from Sharif University of Technology, both in Tehran, Iran. He is currently researching co-designed mechanisms for hardware and system software to improve programmability of multicore systems.
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