Abstract:

Chip multiprocessors (CMPs) commonly share different resources such as large portions of the memory system, total chip energy budget, and execution resources among multiple threads. Improving the efficiency of sharing resources on CMPs enables more cost-efficient consolidation of multiple virtual machines or applications on the same hardware substrate, and can also improve parallel application execution time which enables more important and harder problems to be solved faster.  Since memory requests from different threads executing on different cores significantly interfere with one another in shared memory resources, the design of the shared memory subsystem is crucial for achieving high performance and fairness.

Inter-thread memory system interference has different implications based on the type of workload running on a CMP. In multi-programmed workloads, different applications can experience significantly different slowdowns. If left uncontrolled, large disparities in slowdowns result in low system performance and make system software's priority-based thread scheduling policies ineffective.  In a single multi-threaded application, memory system interference between threads of the same application can slow each thread down significantly. Most importantly, the critical path of execution can also be significantly slowed down, resulting in increased application execution time.

In this talk I will discuss one mechanism which speeds up a single multi-threaded application by managing main-memory related interference between its threads, and another technique that provides fair use of the entire shared memory system among multiple concurrently executing applications thereby improving system performance and fairness.

Bio:

Eiman Ebrahimi is currently a postdoctoral research fellow at the HPS research group of the ECE department at UT Austin. His research interests are primarily in computer architecture and memory systems.  More specifically he is interested in the interactions between runtime systems, operating systems, compilers, and microarchitecture to improve performance, fairness, and energy-efficiency of multi-core architectures. He obtained his PhD (2011) and MS (2007) in ECE from the University of Texas at Austin, and his BS in Computer Engineering from the University of Tehran, Iran. His PhD dissertation was on fair and high performance shared memory resource management for chip multiprocessors.