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Illinois-Intel Parallelism Center (I2PC) Distinguished Speaker Series
Thursday April 26th, 4pm CDT, Room SC3405
UHPC/ExaScale: "There Ain't No Such Thing As A Free Lunch"
The ExaScale machine criteria put forth by DARPA and DoE have set a very aggressive goal for Exa-FLOP computation by 2018 in a 20 MW power budget. No current commercial approach appears to be capable of achieving this design target due to the energy-efficiency barrier. The root causes for failing this future vision encompass the first principles behind circuits, networks, architectures, runtimes, and programming systems. Unless the entire community moves in new directions immediately, no ExaScale machine will be built. This talk will explore what the exact nature of the Ubiquitous High Performance Computing (UHPC) challenge from DARPA requires, starting from measured test chip data on the first principles. The implications of these results imply that many research efforts may be moving in the wrong direction.
Joshua Fryman is the chief CPU architect of Intel's design for the DARPA UHPC challenge. The program was begun in 2010, and confronts the challenges of building potentially Exa-Scale systems on highly constrained energy budgets, problems with resiliency, and the challenge of programmability and usability. He received his B.S. in Computer Engineering from the University of Florida. He spent several years designing cable and satellite TV platforms used by consumers the world over. He then obtained his PhD from Georiga Tech in Computer Architecture before joining Intel as a research scientist. He has been involved in many programs at Intel (Tera-scale research, Larrabee/MIC, Ct, V-ISA, UHPC).
I2PC seminars are held on Thursdays at 4pm Central Time in Room 3405 of the Siebel Center.
They are streamed live at this link:
Questions to the speaker for live response can be posted at:
A complete list of seminars is available here: