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Illinois-Intel Parallelism Center (I2PC) Distinguished Speaker Series: Matt Pharr (Intel)

Speaker Matt Pharr, Intel Corporation
Date Mar 15, 2012
Time 4:00 pm - 5:00 pm   CST
Location 3405 Siebel Center
Cost Free
Sponsor Illinois-Intel Parallelism Center (I2PC)
Contact Meg Osfar
Views 4950
Originating Calendar I2PC Events

Illinois-Intel Parallelism Center (I2PC) Distinguished Speaker Series

Thursday March 15th, 4pm CST, Room SC3405 

 

                                         Matt Pharr

                                      Intel Corporation

 

              ispc: A High-Performance SPMD Compiler for The CPU

 

Abstract:
SIMD parallelism has become an increasingly important mechanism for delivering performance in modern CPUs, due its power efficiency and relatively low cost in die area compared to other forms of parallelism. Unfortunately, languages and compilers for CPUs haven't kept up with the hardware's capabilities.  Existing CPU parallel programming models have almost entirely focused on multicore parallelism, neglecting the substantial computational capabilities available in SIMD vector units, while GPU-oriented languages like OpenCL suffer from constraints that impair ease of use on CPUs and lack capabilities needed to achieve maximum efficiency on CPUs due to their focus on GPU architectures.

This talk describes a new compiler, Intel SPMD Program Compiler (ispc), that delivers very high performance on CPUs thanks to effective use of both processor multiple cores and SIMD vector units.  ispc draws from GPU programming languages, which have shown that for many applications, the easiest way to program SIMD units is to use a single-program, multiple-data (SPMD) model, with one instance of the program mapped to each SIMD lane. This talk will describe discuss language features that make ispc easy to adopt and use productively with existing software systems and present results showing that ispc delivers up to 35x speedups on a 4-core system and up to 240x speedups on a 40-core system for complex workloads compared to serial C++ code.

Bio:
Matt Pharr is a Principal Engineer at Intel where he most recently has built ispc, the Intel SPMD Program Compiler.  He previously was the lead lead graphics architect in the Advanced Rendering Technology group, which researched new interactive graphics algorithms and programming models. Prior to coming to Intel, he co-founded Neoptica, which developed new programming models for graphics on heterogeneous CPU+GPU systems; Neoptica was acquired by Intel. 

Before Neoptica, Matt was in the Software Architecture group at NVIDIA, co-founded Exluna (acquired by NVIDIA), worked in Pixar's Rendering R&D group, and received his Ph.D. from the Stanford Graphics Lab.  With Greg Humphreys, he wrote the textbook "Physically Based Rendering: From Theory to Implementation", which has been used for graduate-level graphics classes at over 20 universities.

 

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I2PC seminars are held on Thursdays at 4pm Central Time in Room 3405 of the Siebel Center.

They are streamed live at this link:

* http://media.cs.illinois.edu/live/I2PClive.asx

Questions to the speaker for live response can be posted at:

* http://i2pc.cs.illinois.edu/chat

A complete list of seminars is available here:

* http://i2pc.cs.illinois.edu/seminars.html