"Creating Chip Generators for Efficient Computing at Low NRE Design Costs"
Changes in technology scaling have made power dissipation today's major performance limiter. The best-known way to improved energy efficiency is application specific customization. However, while many applications could benefit from application-specific chips, industry grade chips are extremely complex systems that require large design teams with experts/expertise in many fields. This makes chip design the purview of a small number of organizations that have the capital and the expertise to succeed. For everyone else it is prohibitively expensive (over $50M on average). In this talk, I will describe my efforts to enable the design of customized computing at manageable costs using "chip generators." The key idea is to enable experts to encode their knowledge and understanding of the complex issues related to creating high performing IC's into an executable form-a generator. Then allow others to use that encapsulated knowledge at the application level.
The first problem we encountered was in the limitations of current hardware description languages. HDLs are sufficient for describing the behavior of a circuit, but weak in encoding the reasoning that led to that particular circuit and architecture choice. To overcome these limitations, we developed Genesis2, a prototype tool for what SystemVerilog (SV) could become. Genesis2 sits atop SV and enables designers to encode their design intent. Today, about 40 users build generators with Genesis2, in academia as well as industry, from mixed signal test chips to arithmetic units, radar applications, network processors, image processors, CMPs and SoCs. A key advantage of generators is design space exploration. I will demonstrate that using FPGen, our floating-point unit generator, which encompasses many years of FP design tricks. We hierarchically created FPGen from lower-level generators for summation trees, Booth encoders, adders, etc. The resultant generator produces cascade and fused multiply-add architectures, for any bit width, across a variety of summation trees, booth encoders, pipelining techniques and pipe depths, and so on. FPGen beats the leading industry libraries by 25-50% in both power and performance. Then, I will further discuss the benefits of a generator at the system level, for generating the validation and software collateral. In particular, I will show empiric results from an 8-core reconfigurable CMP that we designed and taped-out, for how being able to run tests over many hardware configurations exposes design bugs order of magnitude faster.
Ofer Shacham is a Stanford researcher, and is currently running the Specialized Extremely Efficient Computing program at Professor Mark Horowitz's Lab. Shacham is also the founder of Chip Genesis, a company that commercialized the Stanford Chip Generator technologies. Shacham holds master's and PhD degrees from Stanford University, and B.Sc. from Tel Aviv University. His research interests include power efficient, custom and parallel computer architectures, and VLSI design and verification techniques. Prior to his academic career, Shacham had worked for IBM R&D Labs in Israel where he was part of the Xbox360 team. Shacham served as a Sergeant Major in an elite unit in the Israeli Navy.