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Event Detail Information

I2PC Seminar Series - DeNovoND: Efficient Hardware Support for Disciplined Parallelism


Hyojin Sung (University of Illinois)

Date Mar 7, 2013
Time 4:00 pm - 5:00 pm  

Central Time


Siebel Center 2405




Illinois-Intel Parallelism Center


Meg Osfar

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Illinois-Intel Parallelism Center (I2PC) Distinguished Speaker Series

Thursday, March 7th, 4-5pm CST, Siebel Center 2405


       DeNovoND: Efficient Hardware Support for Disciplined Parallelism

                                     Hyojin Sung
                                 University of Illinois

ABSTRACT: Recent work has shown that disciplined shared-memory
programming models that provide deterministic-by-default semantics can
simplify both parallel software and hardware. Specifically, the DeNovo
hardware system has shown that the software guarantees of such models
(e.g., data-race-freedom and explicit side-effects) can enable
simpler, higher performance, and more energy-efficient hardware than
the current state-of-the-art for deterministic programs. Many
applications, however, contain non-deterministic parts; e.g., using
lock synchronization. For commercial hardware to exploit the benefits
of DeNovo, it is therefore necessary to extend DeNovo to support
non-deterministic applications.

This paper proposes DeNovoND, a system that supports lock-based,
disciplined non-determinism, with the simplicity, performance, and
energy benefits of DeNovo. We use a combination of distributed
queue-based locks and access signatures to implement simple memory
consistency semantics for safe non-determinism, with a coherence
protocol that does not require transient states, invalidation traffic,
or directories, and does not incur false sharing. The resulting system
is simpler, shows comparable or better execution time, and has 33%
less network traffic on average (translating directly into energy
savings) relative to a state-of-the-art invalidation-based protocol
for 8 applications designed for lock synchronization.

BIO: Hyojin Sung is a Ph.D student in Computer Science at University
of Illinois, Urbana-Champaign. Her research interests are in parallel
computer architecture, compilers and programming, especially SW/HW
co-design based on parallel programming patterns. She earned her
undergraduate degrees in Literature and Computer Science at Seoul
National University in South Korea and worked for Samsung Electronics
as a research engineer for two years, before she obtained her M.S. in
Computer Science at UC San Diego in 2008 with her thesis on
parallelizing compilers.


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