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Scale-out Energy-efficient Big-data Server: Thousand Cores In-Memory with Reconfigurable I/Os

Event Type
Other
Sponsor
Advanced Digital Sciences Center
Location
ADSC Director's Office
Date
May 30, 2014   2:00 pm  
Speaker
Dr. Yu Hao - Assistant Professor, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
Views
7

Abstract

Big-data analytics has scaled up to Exa-scale (1018 bytes or flops) that is already beyond the scalability of the present technology and architecture. It has thereby raised many new research opportunities to deploy emerging technology and architecture towards building a data-centre on single chip with integrated 1000-core microprocessors and main memory. One fundamental challenge is how to overcome dark silicon dilemma of big-data server with improved I/O utilization for both power management and data communication. The first part of this talk will focus on memory-logic-integration by 3D TSV and 2.5D TSI I/Os with performance comparison from thermal robustness perspective. What is more, a 2.5D reconfigurable I/O architecture is developed for both scalable power management and data communication in many-core microprocessor.  With an adaptive space-time multiplexing depending on data-patterns, the utilization efficiency of energy and bandwidth can be both boosted. The developed 2.5D smart I/O has been utilized in a national big-data server design program to integrate 1000-core accelerators with memory for on-chip machine learning. The remaining part will briefly address the next generation big-data server with logic-in-memory architecture by nano-scale non-volatile memory devices without the use of I/Os.

Speaker Biography

Dr. Hao YU obtained B.S. degree from Fudan University in 1999, and Ph. D degree from UCLA in 2007. Since 2010, he has been an assistant professor at school of electrical and electronic engineering and area director at VIRTUS IC design centre of excellence, Nanyang Technological University (NTU), Singapore. His primary research interest is in CMOS emerging technology and architecture for big-data computing and communication, which has attracted more than 2M USD funding from government and industry. He has 118 peer-reviewed IEEE/ACM publications (DAC/ICCAD/VLSI/CICC), 4 books, 1 best paper award in ACM Transactions, 3 best paper award nominations (DAC’06, ICCAD’06, ASP-DAC’12), 2 student paper competition (advisor) finalist, 1 inventor award from semiconductor research cooperation (SRC-USA), and 5 pending patents. He is associate editor and technical program committee member of many IEEE/ACM international journals and conferences such as ICCAD, ASP-DAC, ISLPED, ICCD, A-SSCC, etc. He is a senior member of IEEE and member of ACM.

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