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PRODID:-//University of Illinois//Web Services Calendar//EN
VERSION:2.0
CALSCALE:GREGORIAN
BEGIN:VEVENT
DTSTAMP:20120214T120900Z
DTSTART;TZID=America/Chicago:20080211T160000
DTEND;TZID=America/Chicago:20080211T160000
SUMMARY:CS Colloquium\, Professor Jose Renau of the University of Califor
 nia at Santa Cruz
CREATED:20071126T120000Z
DESCRIPTION:Title:UCSC MASC Group Thermal and Processor Pruning WorkAbstr
 act:Jose Renau will present the work that his group does at UC-Santa Cru
 z. He will present the current work on real systems infrared thermal mea
 surements and processor pruning.UCSC MASC Group Thermal Work:In order to
  ameliorate some of the difficulties associated with the validation of p
 ower and thermal models\, this work proposes an infrared measurement set
 up to capture run-time power consumption and thermal characteristics of 
 modern chips. We use infrared cameras with high spatial resolution (30x3
 0um) and high frame rate (125fps) to capture thermal maps. We employ gen
 etic algorithms on the maps to generate a detailed power breakdown (leak
 age\, dynamic\, and clock) for each processor floorplan unit. As an exam
 ple of applicability\, we use the obtained measurements to validate CACT
 I and HotLeakage power models\, and propose extensions to existing therm
 al models to increase accuracy.UCSC MASC Group Processor Pruning Work:Th
 e proposed methodology attempts to improve efficiency by helping designe
 rs eliminate extraneous functionality in existing designs\, while ensuri
 ng forward progress in program execution. The designer can then systemat
 ically ``prune'' the HDL code-base of infrequently used functionality in
  an effort to reduce power\, increase frequency\, and reduce area. Forwa
 rd progress can be ensured using previously proposed techniques. Using t
 his methodology\, we exploit increased complexity to expose new avenues 
 for optimization. By applying this technique to an Alpha EV6-like proces
 sor\, it becomes apparent that significant improvements can be realized.
  By removing 3% of infrequently used functionality from the optimistic c
 ore an increase in frequency of 25% can be realized. Taking into account
  the replay overhead triggered by the removed functionality\, the propos
 ed architecture is still able to achieve a 12% overall speedup.
LAST-MODIFIED:20080117T120000Z
LOCATION:1404 Siebel Center
CATEGORIES:Colloquia
ORGANIZER:jdittmar@illinois.edu
URL:http://illinois.edu/calendar/detail/504?key=200001012000010176954
UID:76954@illinois.edu
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